ROC=0, ALT_LOAD=0, UP=0, DBG_EN=00, FAULT=0, OFLAG=0, CL2=00, CL1=00, TCI=0
Timer Channel Comparator Status and Control Register
| CL1 | Compare Load Control 1 0 (00): Never preload 1 (01): Load upon successful compare with the value in COMP1 2 (10): Load upon successful compare with the value in COMP2 |
| CL2 | Compare Load Control 2 0 (00): Never preload 1 (01): Load upon successful compare with the value in COMP1 2 (10): Load upon successful compare with the value in COMP2 |
| TCF1 | Timer Compare 1 Interrupt Flag |
| TCF2 | Timer Compare 2 Interrupt Flag |
| TCF1EN | Timer Compare 1 Interrupt Enable |
| TCF2EN | Timer Compare 2 Interrupt Enable |
| OFLAG | Output flag 0 (0): The OFLAG signal is low. 1 (1): The OFLAG signal is high. |
| UP | Counting Direction Indicator 0 (0): The last count was in the DOWN direction. 1 (1): The last count was in the UP direction. |
| TCI | Triggered Count Initialization Control 0 (0): Stop counter upon receiving a second trigger event while still counting from the first trigger event. 1 (1): Reload the counter upon receiving a second trigger event while still counting from the first trigger event. |
| ROC | Reload on Capture 0 (0): Do not reload the counter on a capture event. 1 (1): Reload the counter on a capture event. |
| ALT_LOAD | Alternative Load Enable 0 (0): Counter can be re-initialized only with the LOAD register. 1 (1): Counter can be re-initialized with the LOAD or CMPLD2 registers depending on count direction. |
| FAULT | Fault Enable 0 (0): Fault function disabled. 1 (1): Fault function enabled. |
| DBG_EN | Debug Actions Enable 0 (00): Continue with normal operation during debug mode. (default) 1 (01): Halt TMR counter during debug mode. 2 (10): Force TMR output to logic 0 (prior to consideration of SCTRL[OPS]). 3 (11): Both halt counter and force output to 0 during debug mode. |